@inbook{f45f8dac1285487bb1f358929efc1c19,
title = "A CMOS Synapse Design Implementing Tunable Asymmetric Spike Timing-Dependent Plasticity",
abstract = " A CMOS synapse design is presented which can perform tunable asymmetric spike timing-dependent learning in asynchronous spiking neural networks. The overall design consists of three primary subcircuit blocks, and the operation of each is described. Pair-based Spike Timing-Dependent Plasticity (STDP) of the entire synapse is then demonstrated through simulation using the Cadence Virtuoso platform. Tuning of the STDP curve learning window and rate of synaptic weight change is possible using various control parameters. With appropriate settings, it is shown the resulting learning rule closely matches that observed in biological systems.",
keywords = "CMOS synapse, neuromorphic design, spike timing-dependent plasticity (STDP)",
author = "Ivans, {Robert C.} and Cantley, {Kurtis D.} and Shumaker, {Justin L.}",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 ; Conference date: 06-08-2017 Through 09-08-2017",
year = "2017",
month = oct,
doi = "10.1109/MWSCAS.2017.8053126",
language = "American English",
series = "1548-3746",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1125--1128",
booktitle = "2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)",
}