TY - GEN
T1 - A novel MEMS based ultra-high density interconnect for wafer-level ultra-thin die stacking technology
AU - Arunasalam, Parthiban
AU - Ackler, Harold D.
AU - Makhar, Sandeep
AU - Sammakia, Bahgat G.
PY - 2005
Y1 - 2005
N2 - The advent of Thru-Silicon-Vias (TSV) has made it possible to distribute I/O in an area array fashion over an ultra-thin silicon chip at less than 20μm in pitch. The wire bonding technique, which is widely used for diestacking technology today cannot support the stacking and interconnection of TSV based ultra-thin chips. The goal of this paper is to present a preliminary version of a Smart Three Axis Compliant (STAC) interconnect for chip-tochip or chip-to-board interconnection suitable for packaging ultra-thin TSV filled dies, in 3D multichip stacks at the wafer level. This MEMS based interconnect will accommodate TCE mismatches between dies within the chip-stackor/and chip-stack to substrate. These flexible interconnects will also enable ultra-thin dies to have 6-degree of freedom movements. Finally the paper will include a preliminary numerical analysis of the STAC interconnect design.
AB - The advent of Thru-Silicon-Vias (TSV) has made it possible to distribute I/O in an area array fashion over an ultra-thin silicon chip at less than 20μm in pitch. The wire bonding technique, which is widely used for diestacking technology today cannot support the stacking and interconnection of TSV based ultra-thin chips. The goal of this paper is to present a preliminary version of a Smart Three Axis Compliant (STAC) interconnect for chip-tochip or chip-to-board interconnection suitable for packaging ultra-thin TSV filled dies, in 3D multichip stacks at the wafer level. This MEMS based interconnect will accommodate TCE mismatches between dies within the chip-stackor/and chip-stack to substrate. These flexible interconnects will also enable ultra-thin dies to have 6-degree of freedom movements. Finally the paper will include a preliminary numerical analysis of the STAC interconnect design.
KW - 3D wafer-level packaging
KW - Compliant interconnect
KW - MEMS
KW - Ultra-high density interconnects
UR - http://www.scopus.com/inward/record.url?scp=84878263168&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84878263168
SN - 9781604235722
T3 - International Microelectronics and Packaging Society - 1st International Conference and Exhibition on Device Packaging 2005: Everything in Electronics Between the Chip and the System
SP - 213
EP - 218
BT - International Microelectronics and Packaging Society - 1st International Conference and Exhibition on Device Packaging 2005
T2 - 1st International Conference and Exhibition on Device Packaging 2005: Everything in Electronics Between the Chip and the System
Y2 - 13 March 2005 through 16 March 2005
ER -