Abstract
In this paper, we investigate the characteristics of the defects responsible for the leakage current in the SiO2 and SiO 2/HfO2 gate dielectric stacks in a wide temperature range (6 K-400 K). We simulated the temperature dependence of the I-V characteristics both at positive and negative gate voltages by applying the multiphonon trap-assisted tunneling model describing the charge transport through the dielectric. In the depletion/weak inversion regime, the current is limited by the supply of carriers available for tunneling. In strong inversion, the temperature dependence is governed by the charge transport mechanisms through the stacks; in particular, in SiO2/HfO2 dielectric stacks, the coupling of the injected carriers with the dielectric phonons at the trap sites is the dominant mechanism. Matching the simulation results to the measurement data allows extracting important trap parameters, e.g., the trap relaxation and ionization energies, which identify the atomic structure of the electrically active defects in the gate dielectric.
Original language | American English |
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Article number | 5948373 |
Pages (from-to) | 2878-2887 |
Number of pages | 10 |
Journal | IEEE Transactions on Electron Devices |
Volume | 58 |
Issue number | 9 |
DOIs | |
State | Published - Sep 2011 |
Keywords
- Dielectric defects
- high-k
- leakage current
- modeling
- oxide reliability
- temperature
- trap assisted tunneling
EGS Disciplines
- Materials Science and Engineering