TY - GEN
T1 - An Ultra-efficient Look-up Table based Programmable Processing in Memory Architecture for Data Encryption
AU - Sutradhar, Purab Ranjan
AU - Basu, Kanad
AU - Dinakarrao, Sai Manoj Pudukotai
AU - Ganguly, Amlan
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - Processing in Memory (PIM), a non-von Neumann computing paradigm, has emerged as a faster and more efficient alternative to the traditional computing devices for data-centric applications such as Data Encryption. In this work, we present a novel PIM architecture implemented using programmable Lookup Tables (LUT) inside a DRAM chip to facilitate massively parallel and ultra-efficient data encryption with the Advanced Encryption Standard (AES) algorithm. Its LUT-based architecture replaces logic-based computations with LUT 'look-ups' to minimize power consumption and operational latency. The proposed PIM architecture is organized as clusters of homogeneous, interconnected LUTs that can be dynamically programmed to execute operations required for performing AES encryption. Our simulations show that the proposed PIM architecture can offer up to 14.6× and 1.8× higher performance compared to CUDA-based implementation of AES Encryption on a high-end commodity GPU and a state-of-the-art GPU Computing Processor, respectively. At the same time, it also achieves 217× and 31.2× higher energy efficiency, respectively, than the aforementioned devices while performing AES Encryption.
AB - Processing in Memory (PIM), a non-von Neumann computing paradigm, has emerged as a faster and more efficient alternative to the traditional computing devices for data-centric applications such as Data Encryption. In this work, we present a novel PIM architecture implemented using programmable Lookup Tables (LUT) inside a DRAM chip to facilitate massively parallel and ultra-efficient data encryption with the Advanced Encryption Standard (AES) algorithm. Its LUT-based architecture replaces logic-based computations with LUT 'look-ups' to minimize power consumption and operational latency. The proposed PIM architecture is organized as clusters of homogeneous, interconnected LUTs that can be dynamically programmed to execute operations required for performing AES encryption. Our simulations show that the proposed PIM architecture can offer up to 14.6× and 1.8× higher performance compared to CUDA-based implementation of AES Encryption on a high-end commodity GPU and a state-of-the-art GPU Computing Processor, respectively. At the same time, it also achieves 217× and 31.2× higher energy efficiency, respectively, than the aforementioned devices while performing AES Encryption.
KW - AES
KW - Data Encryption
KW - DRAM
KW - Processing in Memory
KW - computer architecture
KW - graphics processing units
KW - memory architecture
KW - performance evaluation
KW - power demand
KW - throughput
UR - http://www.scopus.com/inward/record.url?scp=85123918453&partnerID=8YFLogxK
UR - https://doi.org/10.1109/ICCD53106.2021.00049
U2 - 10.1109/ICCD53106.2021.00049
DO - 10.1109/ICCD53106.2021.00049
M3 - Conference contribution
AN - SCOPUS:85123918453
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 252
EP - 259
BT - Proceedings - 2021 IEEE 39th International Conference on Computer Design, ICCD 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 39th IEEE International Conference on Computer Design, ICCD 2021
Y2 - 24 October 2021 through 27 October 2021
ER -