@inproceedings{fe568ccd02de41b5b84d0ca574480f47,
title = "Degradation of rise time in NAND gates using 2.0 nm gate dielectrics",
abstract = "CMOS NAND gate circuit performance degradation caused by a single pMOSFET wearout induced by constant voltage stress in 2.0 nm gate dielectrics is examined using a switch matrix technique. The NAND gate rise time is found to increase by approximately 64%, which may lead to timing errors in high frequency digital circuits. The degraded pMOSFET reveals that a decrease in drive current by 41% and an increase in threshold voltage by 18% are directly proportional to an increase in channel resistance, thereby substantially increasing the NAND gate circuit timing delay.",
author = "Ogas, {M. L.} and Price, {P. M.} and J. Kiepert and Baker, {R. J.} and G. Bersuker and Knowlton, {W. B.}",
year = "2005",
doi = "10.1109/IRWS.2005.1609564",
language = "English",
isbn = "0780389921",
series = "IEEE International Integrated Reliability Workshop Final Report",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "63--66",
booktitle = "2005 IEEE International Integrated Reliability Workshop Final Report, IIRW 2005",
note = "2005 IEEE International Integrated Reliability Workshop, IIRW 2005 ; Conference date: 17-10-2005 Through 20-10-2005",
}