Enhanced Hardware Trojan Detection in Chips By Reducing Linearity Between Features

Alfred Moussa, Nader Rafla

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The growing Internet of Things (IoT) and System on Chip (SoC) applications have increased the prevalence of active medical implants. With the global supply chain issue in Integrated Circuits (ICs), design processes are often outsourced to multiple untrusted entities, creating opportunities for malicious modifications known as Hardware Trojans (HTs). These HTs can compromise integrity, performance, or functionality, and may even introduce backdoors for unauthorized access. This paper presents an enhanced approach for detecting hardware trojans through utilizing Machine Learning models to reduce linearity between features to avoid over-fitting. The supervised model showed a 99.2 % true positive and true negative rate, as well as an F-measure of 99.3%, while the unsupervised model achieved a 99.5% true positive rate with the use of random projection, thereby offering a more resilient machine learning-based method for detecting HT's.

Original languageEnglish
Title of host publication2024 IEEE 67th International Midwest Symposium on Circuits and Systems, MWSCAS 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages985-989
Number of pages5
ISBN (Electronic)9798350387179
DOIs
StatePublished - 2024
Event67th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2024 - Springfield, United States
Duration: 11 Aug 202414 Aug 2024

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Conference

Conference67th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2024
Country/TerritoryUnited States
CitySpringfield
Period11/08/2414/08/24

Keywords

  • Gate-level netlist (G LN)
  • Hardware Trojan (HT)
  • Integrated Circuits (ICs)
  • Machine Learning (ML)
  • System-on-Chip (SoC)

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