TY - GEN
T1 - Enhanced Hardware Trojan Detection in Chips By Reducing Linearity Between Features
AU - Moussa, Alfred
AU - Rafla, Nader
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - The growing Internet of Things (IoT) and System on Chip (SoC) applications have increased the prevalence of active medical implants. With the global supply chain issue in Integrated Circuits (ICs), design processes are often outsourced to multiple untrusted entities, creating opportunities for malicious modifications known as Hardware Trojans (HTs). These HTs can compromise integrity, performance, or functionality, and may even introduce backdoors for unauthorized access. This paper presents an enhanced approach for detecting hardware trojans through utilizing Machine Learning models to reduce linearity between features to avoid over-fitting. The supervised model showed a 99.2 % true positive and true negative rate, as well as an F-measure of 99.3%, while the unsupervised model achieved a 99.5% true positive rate with the use of random projection, thereby offering a more resilient machine learning-based method for detecting HT's.
AB - The growing Internet of Things (IoT) and System on Chip (SoC) applications have increased the prevalence of active medical implants. With the global supply chain issue in Integrated Circuits (ICs), design processes are often outsourced to multiple untrusted entities, creating opportunities for malicious modifications known as Hardware Trojans (HTs). These HTs can compromise integrity, performance, or functionality, and may even introduce backdoors for unauthorized access. This paper presents an enhanced approach for detecting hardware trojans through utilizing Machine Learning models to reduce linearity between features to avoid over-fitting. The supervised model showed a 99.2 % true positive and true negative rate, as well as an F-measure of 99.3%, while the unsupervised model achieved a 99.5% true positive rate with the use of random projection, thereby offering a more resilient machine learning-based method for detecting HT's.
KW - Gate-level netlist (G LN)
KW - Hardware Trojan (HT)
KW - Integrated Circuits (ICs)
KW - Machine Learning (ML)
KW - System-on-Chip (SoC)
UR - https://www.scopus.com/pages/publications/85204956310
U2 - 10.1109/MWSCAS60917.2024.10658816
DO - 10.1109/MWSCAS60917.2024.10658816
M3 - Conference contribution
AN - SCOPUS:85204956310
T3 - Midwest Symposium on Circuits and Systems
SP - 985
EP - 989
BT - 2024 IEEE 67th International Midwest Symposium on Circuits and Systems, MWSCAS 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 67th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2024
Y2 - 11 August 2024 through 14 August 2024
ER -