Gate dielectric degradation effects on nMOS devices using a noise model approach

C. E. Lawrence, B. J. Cheek, T. E. Lawrence, Santosh Kumar, A. Haggag, R. J. Baker, W. B. Knowlton

Research output: Contribution to journalConference articlepeer-review

Abstract

The effects of noise on gate oxide reliability were examined in nMOSCAPs. Noise is modeled as a voltage spike constructively interfering with a carrier signal. This data correlates to the noise model where device lifetime exponentially decreases with an increase in noise voltage. Noise voltages with the same magnitude as the carrier signal voltage decrease the lifetime by as much as three orders of magnitude. For noise that is one-fifth of the magnitude of the carrier signal voltage, an order of magnitude is observed. As interconnect spacing decreases, the probability of noise and capacitive coupling increases; therefore, the effect of noise on the lifetime of MOS devices may be of great concern.

Original languageEnglish
Pages (from-to)263-266
Number of pages4
JournalBiennial University/Government/Industry Microelectronics Symposium - Proceedings
StatePublished - 2003
Event15th Biennial University/Government/Industry Microelectronics Symposium - Boise, ID, United States
Duration: 30 Jun 20032 Jul 2003

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