Hardware Implementation of Image Processing Morphological and Convolution Operations as SoC on FPGAs

Efficient image processing architectures are consistently in demand across a multitude of applications, particularly those customized for resource-constrained systems-on-chip (SoC). The increasing need for high-performance image processing in various sectors has driven the development of specialized architectures. However, deploying such architectures on platforms with limited resources, such as SoCs, poses significant challenges. Furthermore, the implementation of complex algorithms to handle large datasets using software solutions often leads to slower response times, prompting exploration into hardware implementations. Field-Programmable Gate Arrays (FPGAs) are becoming popular for hardware implementations because of their attributes: low latency, connectivity, parallel computing capabilities, and flexibility. Consequently, the utilization of FPGA-based implementations has resulted in faster and more efficient performance of unique architectures tailored to specific requirements. This paper presents a novel hardware/software co-design approach to implement erosion, dilation, and neighborhood image processing operations on the FPGA development board, "Zedboard". In this approach, the FPGA is programmed by connecting it to a PC via USB, facilitating the transfer of an image pixel by pixel. The pixels are temporarily stored in on-chip DDR and accessed through DMA (Direct Memory Access) until they are requested by an interrupt signal from the Image Processing IP, at which point they are moved to line buffers for faster processing. Once processed, the image is transmitted back to the PC via UART, facilitating pixel-by-pixel transfer for verification, where it is compared with a reference image generated using Python. This comparison confirms a 99.22% match between the processed image and the reference image, with the discrepancy occurring at the image's edges due to initial padding. Additionally, the time required to process the entire image was measured and displayed on an OLED for timing verification. which processing time amounted to 2.652 ms which is faster than other related hardware implementation.