High-level synthesis optimization of AES-128/192/256 encryption algorithms

Advanced Encryption Standard (AES) is applied in many worldwide systems including several private and public sectors to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. AES encryption algorithm is composed of several functions and serial rounds which makes it challenge to be efficiently implemented and optimized in hardware. As a solution, High-Level Synthesis (HLS) offers flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we designed a fully pipelined AES encryption engine for key sizes, 128, 192, and 256 using Xilinx Vivado HLS tool chain. The AES architecture was designed and pipelined such that an encryption process is executed every clock cycle after filling the pipeline latency. We show that the proposed HLS-based design achieves 28 Gbps (Gigabit per second) throughput on Artix-7 FPGA occupying 2794, 3306, and 3750 FPGA-slices for AES-128, AES-192, and AES-256, respectively.