@inproceedings{30e1e8048b984df9938b253ce9cbfbaa,
title = "High level synthesis using vivado HLS for optimizations of SHA-3",
abstract = "Hash functions represent a fundamental building block of many network security protocols. The SHA-3 hashing algorithm is the most recently developed hash function, and the most secure. Implementation of the SHA-3 hashing algorithm in Hardware Description Language (HDL) is time demanding and tedious to debug. On the other hand, High-Level Synthesis (HLS) tools offer potential solutions to the hardware design. HLS tools provide us with advanced capabilities for design evaluation and a wide variety of optimization techniques. In this paper, the SHA-3 hashing algorithm and its implementation onto a Xilinx{\textregistered} Zynq-7000 SoPC is explored. The SHA-3 hashing algorithm is initially coded in C programming language and then implemented with Xilinx Vivado HLS. The HLS tool enabled us to quickly analyze our design to make suitable optimizations which led to increased throughput of the SHA-3 hashing algorithm, up to 2000 Mbps. After pipelining the synthesized hardware design, it was capable of hashing a block of 1088 bits in 70 clock cycles.",
keywords = "FPGA, Hardware Implementation, Hash Algorithm, High-level Synthesis, HLS, Keccak, Pipeline, SHA-3, Vivado, ZedBoard",
author = "Jacinto, {H. S.} and Luka Daoud and Nader Rafla",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 ; Conference date: 06-08-2017 Through 09-08-2017",
year = "2017",
month = sep,
day = "27",
doi = "10.1109/MWSCAS.2017.8052985",
language = "English",
series = "Midwest Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "563--566",
booktitle = "2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017",
}