HLS implementation of linear discriminant analysis classifier

Michael R. Wasef, Nader Rafla

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Data classification has improved significantly over time and nowadays is used in a variety of purposes and applications. This paper demonstrates the design and implementation of multivariate classifier linear discriminant algorithm on a Field Programable Gate Array (FPGA) as System on Chip (SoC). The classifier is optimized using High Level Synthesis (HLS) techniques. The optimized design is placed on the programmable logic part of the chip while its controller is built on the embedded processor of the same chip. The paper details the process of the classifier design and optimization and reports on the power consumption, resource utilization, latency, and algorithm accuracy before and after optimization.

Original languageEnglish
Title of host publication2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728133201
DOIs
StatePublished - 2020
Event52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online
Duration: 10 Oct 202021 Oct 2020

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2020-October
ISSN (Print)0271-4310

Conference

Conference52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
CityVirtual, Online
Period10/10/2021/10/20

Keywords

  • Data classification
  • FPGA
  • High level synthesis
  • HLS
  • LDA
  • Linear discriminant analysis
  • SOC

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