TY - JOUR
T1 - Impact of single pMOSFET dielectric degradation on NAND circuit performance
AU - Estrada, D.
AU - Ogas, M. L.
AU - Southwick, R. G.
AU - Price, P. M.
AU - Baker, R. J.
AU - Knowlton, W. B.
PY - 2008/3
Y1 - 2008/3
N2 - Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source-to-drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.
AB - Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source-to-drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.
UR - http://www.scopus.com/inward/record.url?scp=39549099285&partnerID=8YFLogxK
U2 - 10.1016/j.microrel.2007.09.002
DO - 10.1016/j.microrel.2007.09.002
M3 - Article
AN - SCOPUS:39549099285
SN - 0026-2714
VL - 48
SP - 354
EP - 363
JO - Microelectronics Reliability
JF - Microelectronics Reliability
IS - 3
ER -