TY - GEN
T1 - Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware
AU - Das, Prangon
AU - Sutradhar, Purab Ranjan
AU - Indovina, Mark
AU - Dinakarrao, Sai Manoj Pudukotai
AU - Ganguly, Amlan
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Deep Neural Networks (DNNs) are often associated with a large number of data-parallel computations. Therefore, data-centric computing paradigms, such as Processing in Memory (PIM), are being widely explored for DNN acceleration applications. A recent PIM architecture, developed and commercialized by the UPMEM company, has demonstrated impressive performance boost over traditional CPU-based systems for a wide range of data-parallel applications. However, the application domain of DNN acceleration is yet to be explored on this PIM platform. In this work, we present successful implementations of DNNs on the UPMEM PIM system. We explore multiple operation mapping schemes with different optimization goals and accelerate two CNN algorithms using these schemes. Based on the data achieved from the physical implementation of the DNNs on the UPMEM system, we compare the performance of our DNN implementation with several other recently proposed PIM architecture.
AB - Deep Neural Networks (DNNs) are often associated with a large number of data-parallel computations. Therefore, data-centric computing paradigms, such as Processing in Memory (PIM), are being widely explored for DNN acceleration applications. A recent PIM architecture, developed and commercialized by the UPMEM company, has demonstrated impressive performance boost over traditional CPU-based systems for a wide range of data-parallel applications. However, the application domain of DNN acceleration is yet to be explored on this PIM platform. In this work, we present successful implementations of DNNs on the UPMEM PIM system. We explore multiple operation mapping schemes with different optimization goals and accelerate two CNN algorithms using these schemes. Based on the data achieved from the physical implementation of the DNNs on the UPMEM system, we compare the performance of our DNN implementation with several other recently proposed PIM architecture.
KW - Deep Neural Network
KW - Processing in Memory
KW - Real-system Characterization
UR - http://www.scopus.com/inward/record.url?scp=85140774930&partnerID=8YFLogxK
U2 - 10.1109/SOCC56010.2022.9908126
DO - 10.1109/SOCC56010.2022.9908126
M3 - Conference contribution
T3 - International System on Chip Conference
BT - 2022 IEEE 35th International System-on-Chip Conference (SOCC)
A2 - Sezer, Sakir
A2 - Buchner, Thomas
A2 - Becker, Jurgen
A2 - Marshall, Andrew
A2 - Siddiqui, Fahad
A2 - Harbaum, Tanja
A2 - McLaughlin, Kieran
PB - IEEE Computer Society
T2 - 35th IEEE International System-on-Chip Conference, SOCC 2022
Y2 - 5 September 2022 through 8 September 2022
ER -