TY - JOUR
T1 - Integrating Through-Wafer Interconnects with Active Devices and Circuits
AU - Jozwiak, Jim
AU - Southwick, Richard G.
AU - Johnson, Vaughn N.
AU - Knowlton, William B.
AU - Moll, Amy J.
PY - 2008/2/1
Y1 - 2008/2/1
N2 - Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options for creating TWIs were considered. This paper explores the various processing options and describes in detail, the final process flow that was selected for testing, the accompanying masks that were designed, the actual processing of the wafers, and the electrical test results.
AB - Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options for creating TWIs were considered. This paper explores the various processing options and describes in detail, the final process flow that was selected for testing, the accompanying masks that were designed, the actual processing of the wafers, and the electrical test results.
KW - integrated circuit interconnections
KW - wafer level packaging
UR - https://scholarworks.boisestate.edu/electrical_facpubs/57
U2 - 10.1109/TADVP.2007.906235
DO - 10.1109/TADVP.2007.906235
M3 - Article
JO - IEEE Transactions on Advanced Packaging
JF - IEEE Transactions on Advanced Packaging
ER -