Investigation of tunneling current in SiO2/HfO2 gate stacks for flash memory applications

Bhaswar Chakrabarti, Heesoo Kang, Barry Brennan, Tae Joo Park, Kurtis D. Cantley, Adam Pirkle, Stephen McDonnell, Jiyoung Kim, Robert M. Wallace, Eric M. Vogel

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO2/HfO2 gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO2 is not suitable for use in SiO2/HfO 2 stacks for tunnel barrier engineering applications. The performance of SiO2/HfO2 stacks improves with decreasing thickness of the HfO2 layer. Mild (10%) O2/N2 anneals do not significantly affect performance, although annealing above 600 °C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO 2/HfO2 stacks.

Original languageEnglish
Article number6062399
Pages (from-to)4189-4195
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume58
Issue number12
DOIs
StatePublished - Dec 2011

Keywords

  • Charge traps
  • Fowler-Nordheim (F-N) tunneling
  • high-k dielectric
  • tunnel barrier engineering
  • high-$k$ dielectric

EGS Disciplines

  • Electrical and Computer Engineering

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