TY - JOUR
T1 - Investigation of tunneling current in SiO2/HfO2 gate stacks for flash memory applications
AU - Chakrabarti, Bhaswar
AU - Kang, Heesoo
AU - Brennan, Barry
AU - Park, Tae Joo
AU - Cantley, Kurtis D.
AU - Pirkle, Adam
AU - McDonnell, Stephen
AU - Kim, Jiyoung
AU - Wallace, Robert M.
AU - Vogel, Eric M.
PY - 2011/12
Y1 - 2011/12
N2 - Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO2/HfO2 gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO2 is not suitable for use in SiO2/HfO 2 stacks for tunnel barrier engineering applications. The performance of SiO2/HfO2 stacks improves with decreasing thickness of the HfO2 layer. Mild (10%) O2/N2 anneals do not significantly affect performance, although annealing above 600 °C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO 2/HfO2 stacks.
AB - Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO2/HfO2 gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO2 is not suitable for use in SiO2/HfO 2 stacks for tunnel barrier engineering applications. The performance of SiO2/HfO2 stacks improves with decreasing thickness of the HfO2 layer. Mild (10%) O2/N2 anneals do not significantly affect performance, although annealing above 600 °C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO 2/HfO2 stacks.
KW - Charge traps
KW - Fowler-Nordheim (F-N) tunneling
KW - high-k dielectric
KW - tunnel barrier engineering
KW - high-$k$ dielectric
UR - http://www.scopus.com/inward/record.url?scp=82155168203&partnerID=8YFLogxK
UR - http://dx.doi.org/10.1109/TED.2011.2170198
U2 - 10.1109/TED.2011.2170198
DO - 10.1109/TED.2011.2170198
M3 - Article
AN - SCOPUS:82155168203
SN - 0018-9383
VL - 58
SP - 4189
EP - 4195
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 12
M1 - 6062399
ER -