Investigation of tunneling current in SiO2/HfO2 gate stacks for flash memory applications

Bhaswar Chakrabarti; Heesoo Kang; Barry Brennan; Tae Joo Park; Kurtis D. Cantley; Adam Pirkle; Stephen McDonnell; Jiyoung Kim; Robert M. Wallace; Eric M. Vogel

doi:10.1109/TED.2011.2170198

Investigation of tunneling current in SiO₂/HfO₂ gate stacks for flash memory applications

Bhaswar Chakrabarti
, Heesoo Kang
, Barry Brennan
, Tae Joo Park
, Kurtis D. Cantley
, Adam Pirkle
, Stephen McDonnell
, Jiyoung Kim
, Robert M. Wallace
, Eric M. Vogel

Electrical Engineering Department

University of Texas at Dallas
Samsung
Hanyang University
Intel
Georgia Institute of Technology

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO₂/HfO₂ gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO₂ is not suitable for use in SiO₂/HfO ₂ stacks for tunnel barrier engineering applications. The performance of SiO₂/HfO₂ stacks improves with decreasing thickness of the HfO₂ layer. Mild (10%) O₂/N₂ anneals do not significantly affect performance, although annealing above 600 °C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO ₂/HfO₂ stacks.

Original language	English
Article number	6062399
Pages (from-to)	4189-4195
Number of pages	7
Journal	IEEE Transactions on Electron Devices
Volume	58
Issue number	12
DOIs	https://doi.org/10.1109/TED.2011.2170198
State	Published - Dec 2011

Keywords

Charge traps
Fowler-Nordheim (F-N) tunneling
high-k dielectric
tunnel barrier engineering
high-$k$ dielectric

EGS Disciplines

Electrical and Computer Engineering

Access to Document

10.1109/TED.2011.2170198

Cite this

@article{70df9f9f81af483eae9fc4285c486b13,

title = "Investigation of tunneling current in SiO2/HfO2 gate stacks for flash memory applications",

abstract = "Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO2/HfO2 gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO2 is not suitable for use in SiO2/HfO 2 stacks for tunnel barrier engineering applications. The performance of SiO2/HfO2 stacks improves with decreasing thickness of the HfO2 layer. Mild (10\%) O2/N2 anneals do not significantly affect performance, although annealing above 600 °C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO 2/HfO2 stacks.",

keywords = "Charge traps, Fowler-Nordheim (F-N) tunneling, high-k dielectric, tunnel barrier engineering, high-\$k\$ dielectric",

author = "Bhaswar Chakrabarti and Heesoo Kang and Barry Brennan and Park, \{Tae Joo\} and Cantley, \{Kurtis D.\} and Adam Pirkle and Stephen McDonnell and Jiyoung Kim and Wallace, \{Robert M.\} and Vogel, \{Eric M.\}",

year = "2011",

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doi = "10.1109/TED.2011.2170198",

language = "English",

volume = "58",

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T1 - Investigation of tunneling current in SiO2/HfO2 gate stacks for flash memory applications

AU - Chakrabarti, Bhaswar

AU - Kang, Heesoo

AU - Brennan, Barry

AU - Park, Tae Joo

AU - Cantley, Kurtis D.

AU - Pirkle, Adam

AU - McDonnell, Stephen

AU - Kim, Jiyoung

AU - Wallace, Robert M.

AU - Vogel, Eric M.

PY - 2011/12

Y1 - 2011/12

N2 - Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO2/HfO2 gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO2 is not suitable for use in SiO2/HfO 2 stacks for tunnel barrier engineering applications. The performance of SiO2/HfO2 stacks improves with decreasing thickness of the HfO2 layer. Mild (10%) O2/N2 anneals do not significantly affect performance, although annealing above 600 °C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO 2/HfO2 stacks.

AB - Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO2/HfO2 gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO2 is not suitable for use in SiO2/HfO 2 stacks for tunnel barrier engineering applications. The performance of SiO2/HfO2 stacks improves with decreasing thickness of the HfO2 layer. Mild (10%) O2/N2 anneals do not significantly affect performance, although annealing above 600 °C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO 2/HfO2 stacks.

KW - Charge traps

KW - Fowler-Nordheim (F-N) tunneling

KW - high-k dielectric

KW - tunnel barrier engineering

KW - high-$k$ dielectric

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