Leakage Current Recovery in SRAM After AC Stressing

C. Payan, S. Kumar, A. Thupil, S. Kasichainula, W. B. Knowlton

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A recovery of sub-threshold current, measured as standby current has been seen on static random access memory (SRAM) devices after AC stress. A theoretical model is presented to explain the observed data in this paper. A trapped charge model is proposed for decrease in subthreshold current leading to lower observed standby current on continuous negative unipolar write stress. Several mechanisms have been proposed earlier such as Poole-Frenkel enhanced emission from traps, trap assisted tunneling, and band-to-band tunneling to explain possible source of off current.

Original languageAmerican English
Title of host publication2003 IEEE International Integrated Reliability Workshop Final Report
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages67-70
Number of pages4
ISBN (Electronic)0780381572
DOIs
StatePublished - 2003
Event2003 IEEE International Integrated Reliability Workshop, IRW 2003 - Lake Tahoe, United States
Duration: 20 Oct 200323 Oct 2003

Publication series

NameIEEE International Integrated Reliability Workshop Final Report
Volume2003-January
ISSN (Print)1930-8841
ISSN (Electronic)2374-8036

Conference

Conference2003 IEEE International Integrated Reliability Workshop, IRW 2003
Country/TerritoryUnited States
CityLake Tahoe
Period20/10/0323/10/03

Keywords

  • CMOS process
  • CMOS technology
  • Current measurement
  • Electron traps
  • Leakage current
  • Random access memory
  • Stress
  • Variable structure systems
  • Voltage
  • Writing

EGS Disciplines

  • Electrical and Computer Engineering

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