Nonvolatile quantum dot memory (NVQDM) in floating gate configuration: Device and circuit modeling

E. S. Hasaneen; A. Rodriguez; B. Yarlagadda; F. Jain; E. Heller; W. Huang; J. Lee; F. Papadimitrakopoulos

doi:10.1109/NANO.2003.1231019

Nonvolatile quantum dot memory (NVQDM) in floating gate configuration: Device and circuit modeling

E. S. Hasaneen, A. Rodriguez, B. Yarlagadda, F. Jain, E. Heller, W. Huang, J. Lee, F. Papadimitrakopoulos

Chemistry Department

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

In this paper, we describe the physical and circuit models of a nonvolatile memory cell comprising of CdSe nanocrystals in a floating gate configuration. The floating gate voltage is computed from the ratio of capacitances between the floating gate and control gate. Threshold voltage for the 0.07 μm channel length MOSFET is calculated using various device parameters including the effect of charge on nanocrystal quantum dots. Current voltage characteristics are obtained using BSIM3v3. The gate current is modeled based on direct tunneling between the channel and nanocrystals. Results for a 70 nm channel length device are presented.

Original language	English
Title of host publication	2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - Proceedings
Publisher	IEEE Computer Society
Pages	741-744
Number of pages	4
ISBN (Electronic)	0780379764
DOIs	https://doi.org/10.1109/NANO.2003.1231019
State	Published - 2003
Event	2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - San Francisco, United States Duration: 12 Aug 2003 → 14 Aug 2003

Publication series

Name	Proceedings of the IEEE Conference on Nanotechnology
Volume	2
ISSN (Print)	1944-9399
ISSN (Electronic)	1944-9380

Conference

Conference	2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003
Country/Territory	United States
City	San Francisco
Period	12/08/03 → 14/08/03

Keywords

Circuits
MOSFETs
Nanocrystals
Nonvolatile memory
Quantum capacitance
Quantum dots
Threshold voltage
Tunneling
US Department of Transportation
Voltage control

Access to Document

10.1109/NANO.2003.1231019

Cite this

Hasaneen, E. S., Rodriguez, A., Yarlagadda, B., Jain, F., Heller, E., Huang, W., Lee, J., & Papadimitrakopoulos, F. (2003). Nonvolatile quantum dot memory (NVQDM) in floating gate configuration: Device and circuit modeling. In 2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - Proceedings (pp. 741-744). Article 1231019 (Proceedings of the IEEE Conference on Nanotechnology; Vol. 2). IEEE Computer Society. https://doi.org/10.1109/NANO.2003.1231019

@inproceedings{22a35955784d455a8aab59ac5e23a682,

title = "Nonvolatile quantum dot memory (NVQDM) in floating gate configuration: Device and circuit modeling",

abstract = "In this paper, we describe the physical and circuit models of a nonvolatile memory cell comprising of CdSe nanocrystals in a floating gate configuration. The floating gate voltage is computed from the ratio of capacitances between the floating gate and control gate. Threshold voltage for the 0.07 μm channel length MOSFET is calculated using various device parameters including the effect of charge on nanocrystal quantum dots. Current voltage characteristics are obtained using BSIM3v3. The gate current is modeled based on direct tunneling between the channel and nanocrystals. Results for a 70 nm channel length device are presented.",

keywords = "Circuits, MOSFETs, Nanocrystals, Nonvolatile memory, Quantum capacitance, Quantum dots, Threshold voltage, Tunneling, US Department of Transportation, Voltage control",

author = "Hasaneen, {E. S.} and A. Rodriguez and B. Yarlagadda and F. Jain and E. Heller and W. Huang and J. Lee and F. Papadimitrakopoulos",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 ; Conference date: 12-08-2003 Through 14-08-2003",

year = "2003",

doi = "10.1109/NANO.2003.1231019",

language = "English",

series = "Proceedings of the IEEE Conference on Nanotechnology",

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Hasaneen, ES, Rodriguez, A, Yarlagadda, B, Jain, F, Heller, E, Huang, W, Lee, J & Papadimitrakopoulos, F 2003, Nonvolatile quantum dot memory (NVQDM) in floating gate configuration: Device and circuit modeling. in 2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - Proceedings., 1231019, Proceedings of the IEEE Conference on Nanotechnology, vol. 2, IEEE Computer Society, pp. 741-744, 2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003, San Francisco, United States, 12/08/03. https://doi.org/10.1109/NANO.2003.1231019

Nonvolatile quantum dot memory (NVQDM) in floating gate configuration: Device and circuit modeling. / Hasaneen, E. S.; Rodriguez, A.; Yarlagadda, B. et al.
2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - Proceedings. IEEE Computer Society, 2003. p. 741-744 1231019 (Proceedings of the IEEE Conference on Nanotechnology; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Hasaneen, E. S.

AU - Rodriguez, A.

AU - Yarlagadda, B.

AU - Jain, F.

AU - Heller, E.

AU - Huang, W.

AU - Lee, J.

AU - Papadimitrakopoulos, F.

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N2 - In this paper, we describe the physical and circuit models of a nonvolatile memory cell comprising of CdSe nanocrystals in a floating gate configuration. The floating gate voltage is computed from the ratio of capacitances between the floating gate and control gate. Threshold voltage for the 0.07 μm channel length MOSFET is calculated using various device parameters including the effect of charge on nanocrystal quantum dots. Current voltage characteristics are obtained using BSIM3v3. The gate current is modeled based on direct tunneling between the channel and nanocrystals. Results for a 70 nm channel length device are presented.

AB - In this paper, we describe the physical and circuit models of a nonvolatile memory cell comprising of CdSe nanocrystals in a floating gate configuration. The floating gate voltage is computed from the ratio of capacitances between the floating gate and control gate. Threshold voltage for the 0.07 μm channel length MOSFET is calculated using various device parameters including the effect of charge on nanocrystal quantum dots. Current voltage characteristics are obtained using BSIM3v3. The gate current is modeled based on direct tunneling between the channel and nanocrystals. Results for a 70 nm channel length device are presented.

KW - Circuits

KW - MOSFETs

KW - Nanocrystals

KW - Nonvolatile memory

KW - Quantum capacitance

KW - Quantum dots

KW - Threshold voltage

KW - Tunneling

KW - US Department of Transportation

KW - Voltage control

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Hasaneen ES, Rodriguez A, Yarlagadda B, Jain F, Heller E, Huang W et al. Nonvolatile quantum dot memory (NVQDM) in floating gate configuration: Device and circuit modeling. In 2003 3rd IEEE Conference on Nanotechnology, IEEE-NANO 2003 - Proceedings. IEEE Computer Society. 2003. p. 741-744. 1231019. (Proceedings of the IEEE Conference on Nanotechnology). doi: 10.1109/NANO.2003.1231019

Nonvolatile quantum dot memory (NVQDM) in floating gate configuration: Device and circuit modeling

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