@inproceedings{c650de5a20e24460a2b54cd9bc2bcb5d,
title = "Optimization of advanced encryption standard (AES) using vivado high level synthesis (HLS)",
abstract = "Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.",
keywords = "Advanced encryption standard, AES, FPGA, High level synthesis, High throughput, HLS, Low area resources, Optimization, Zynq",
author = "Luka Daoud and Fady Hussein and Nader Rafla",
note = "Publisher Copyright: Copyright {\textcopyright} 2012-2020 easychair.org. All rights reserved.; 34th International Conference on Computers and Their Applications, CATA 2019 ; Conference date: 18-03-2019 Through 20-03-2019",
year = "2019",
month = mar,
day = "13",
language = "English",
series = "Proceedings of 34th International Conference on Computers and Their Applications, CATA 2019",
pages = "36--44",
editor = "Gordon Lee and Ying Jin",
booktitle = "Proceedings of 34th International Conference on Computers and Their Applications, CATA 2019",
}