Optimization of Bosch etch process for through wafer interconnects

Linda Kenoyer; Rex Oxford; Amy Moll

Optimization of Bosch etch process for through wafer interconnects

Linda Kenoyer, Rex Oxford, Amy Moll

Micron School of Materials Science and Engineering

Boise State University

Research output: Contribution to journal › Conference article › peer-review

11 Scopus citations

Abstract

The Bosch etch process¹ was utilized to create 50 micrometer vias with an aspect ration of 10:1 in silicon wafers for through wafer interconnects. The process is complex with twenty-two separate parameters required to control the process. Deviating from the standard process and flowing SF₆ during the deposition process resulted in a more stable and reproducible process.

Original language	English
Pages (from-to)	338-339
Number of pages	2
Journal	Biennial University/Government/Industry Microelectronics Symposium - Proceedings
State	Published - 2003
Event	15th Biennial University/Government/Industry Microelectronics Symposium - Boise, ID, United States Duration: 30 Jun 2003 → 2 Jul 2003

Cite this

@article{5867de69097046caae625a63915ba7c8,

title = "Optimization of Bosch etch process for through wafer interconnects",

abstract = "The Bosch etch process1 was utilized to create 50 micrometer vias with an aspect ration of 10:1 in silicon wafers for through wafer interconnects. The process is complex with twenty-two separate parameters required to control the process. Deviating from the standard process and flowing SF6 during the deposition process resulted in a more stable and reproducible process.",

author = "Linda Kenoyer and Rex Oxford and Amy Moll",

year = "2003",

language = "English",

pages = "338--339",

note = "15th Biennial University/Government/Industry Microelectronics Symposium ; Conference date: 30-06-2003 Through 02-07-2003",

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TY - JOUR

T1 - Optimization of Bosch etch process for through wafer interconnects

AU - Kenoyer, Linda

AU - Oxford, Rex

AU - Moll, Amy

PY - 2003

Y1 - 2003

N2 - The Bosch etch process1 was utilized to create 50 micrometer vias with an aspect ration of 10:1 in silicon wafers for through wafer interconnects. The process is complex with twenty-two separate parameters required to control the process. Deviating from the standard process and flowing SF6 during the deposition process resulted in a more stable and reproducible process.

AB - The Bosch etch process1 was utilized to create 50 micrometer vias with an aspect ration of 10:1 in silicon wafers for through wafer interconnects. The process is complex with twenty-two separate parameters required to control the process. Deviating from the standard process and flowing SF6 during the deposition process resulted in a more stable and reproducible process.

UR - https://www.scopus.com/pages/publications/0041939914

M3 - Conference article

AN - SCOPUS:0041939914

SN - 0749-6877

SP - 338

EP - 339

JO - Biennial University/Government/Industry Microelectronics Symposium - Proceedings

JF - Biennial University/Government/Industry Microelectronics Symposium - Proceedings

T2 - 15th Biennial University/Government/Industry Microelectronics Symposium

Y2 - 30 June 2003 through 2 July 2003

ER -

Optimization of Bosch etch process for through wafer interconnects

Abstract

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