POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications

Sathwika Bavikadi, Purab Ranjan Sutradhar, Mark A. Indovina, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

Improving the performance of real-time Traffic Sign Recognition (TSR) applications using Deep Learning (DL) algorithms such as Convolutional Neural Networks (CNN) on software platforms is challenging due to the sheer computational complexity of these algorithms. In this work, we adopt a hardware-software combined approach to address this issue. We introduce a data-centric Processing-in-Memory (PIM) architecture that leverages Look-up-Table (LUT)-based processing for minimal data movement and superior performance and efficiency. Despite the superior performance, the limited available memory in PIM makes it complex to deploy deep CNNs. We propose merging CNN layers in this work to meet the limited resource constraints. One specific challenge in the TSR is the continuous change in the deployed environment, which makes a CNN model train over static data, leading to performance degradation over time. To address these challenges, we introduce a lightweight, performance-aware Generative Adversarial Network (GAN)-based on-device learning on PIM architecture. This compact CNN on PIM architecture attains data-level parallelism and reduces pipelining delays and makes it easier for on-device training and inference. Evaluation is performed on multiple state-of-the-art DL networks such as LeNet, AlexNet, ResNet using the German Traffic Sign Recognition Benchmark (GTSRB) Dataset, and the Belgium Traffic Sign Dataset (BTSD). With the proposed learning technique, it is observed to achieve maximum accuracy of 92.8% and 89.27% on GTSRB, and BTSD datasets. Also, it is observed the proposed mechanism maintains an average accuracy to be above 85% despite changes in the environment on all the CNNs deployed on the PIM accelerator.

Original languageEnglish
Title of host publicationProceedings - 2022 25th Euromicro Conference on Digital System Design, DSD 2022
EditorsHimar Fabelo, Samuel Ortega, Amund Skavhaug
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages889-898
Number of pages10
ISBN (Electronic)9781665474047
DOIs
StatePublished - 2022
Event25th Euromicro Conference on Digital System Design, DSD 2022 - Maspalomas, Spain
Duration: 31 Aug 20222 Sep 2022

Publication series

NameProceedings - 2022 25th Euromicro Conference on Digital System Design, DSD 2022

Conference

Conference25th Euromicro Conference on Digital System Design, DSD 2022
Country/TerritorySpain
CityMaspalomas
Period31/08/222/09/22

Keywords

  • Convolutional Neural Network
  • Look-up-Table
  • Processing-in-Memory

EGS Disciplines

  • Electrical and Computer Engineering

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