Abstract
The future of critical health diagnosis will involve intelligent and smart devices that are low-cost, wearable, and lightweight requiring power efficient hardware platforms. Various machine learning (ML) models such as deep learning architectures have been employed in the design of intelligent systems. However, the deployment of such systems on edge devices with limited hardware resources and power budget is difficult due to the requirement of high computational power and system accuracy. As a result, this creates a significant gap between the advancement of computing technology and the associated device technologies for healthcare applications. To address such issue, this research introduces power efficient ML based digital hardware design technique for a compact design solution while maintaining its optimal prediction accuracy. A hardware design approach called SABiNN: Shift-Accumulate Based binarized Neural Network is proposed and developed which is a 2’s complement based binarized digital hardware technique. Neural network (NN) models such as feedforward FCNN models were selected to analyze and validate the proposed method. Deep compression learning techniques for hardware implementation such as n-bit integer quantization, and deterministic binarization on the model’s hyper-parameters were also employed. Instead of using matrix multiplication based multiply accumulate (MAC) function typically used in hardware accelerators, shifters and 2’s complements were introduced which significantly reduced the power consumption rate by 5x times. On CMOS platform, XNOR gates were re-designed with NAND gates which significantly reduced signal noise and increased precision rate. Moreover, during inference there were no need of internal nor external memory devices for storing the networks’ weights and biases due to fixed hyper-parametric values. As a result, the processing power and model size were significantly reduced. For efficient use of the SABiNN method in biomedical applications, system architecture of a sleep apnea (SA) detection device is proposed which can detect SA events in real-time. The input to the system consists of two biosensor data such as ECG signal from the chest movement and SpO2 measurement from finger-tip pulse oximeter. In the training phase, open-source real patient datasets were used from PhysioNET bank. The proposed hardware model achieved a targeted accuracy of 81.5% (CI: 3.5%) which is medically acceptable and realistic. During inference, all the parameters were successfully extracted, and each component was designed into re-programmable hardware before translated onto CMOS platform. General-purpose Nexys Artix-7 FPGA was used for hardware model validation and the final post-trained model was integrated on CMOS platform using both 130nm and 180nm design processes. A three hidden layer NN model was design on re-programmable hardware with 8-bit input and 1-bit output channels. The model was further expanded on silicon as a 4-layer hidden model with 16-bit input and 1-bit output channels which also increased the model accuracy to 88%. Activation functions such as Rectified Linear Unit (ReLU) was used on the hidden layers and hard sigmoid function was used at the output layer where both functions were designed using stacked 2:1 multiplexer. The final power consumption rate of the model resulted in ~5W (5mJ) with 10ms clock delay on re-programmable hardware and ~10uW (1nJ) with 10ns clock delay on silicon. The success of this design technique can be leveraged in developing a fully system-on-a-chip (SoC) integrated biomedical system for wearable applications.
Original language | American English |
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State | Published - 30 Nov 2022 |
Externally published | Yes |
Event | TinyML Asia Technical Forum 2022 - Virtual Duration: 30 Nov 2022 → … |
Conference
Conference | TinyML Asia Technical Forum 2022 |
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Period | 30/11/22 → … |
Keywords
- TinyML hardware techniques
- design ideas
- silicon implementations
EGS Disciplines
- Electrical and Computer Engineering