@inproceedings{a9f4ee42968f4dc4b8443aefec72e7c5,
title = "Preliminary study of NOR digital response to single pMOSFET dielectric degradation",
abstract = "The voltage-time domain (VT) characteristics of the CMOS NOR logic circuit are investigated using a switch matrix technique (SMT). VT performance is analyzed following gate oxide wearout in a pMOSFET, induced by applying a constant voltage stress (CVS) at -4.0 V. Results for the NOR VT characteristics show approximately 30% increase in rise time (tr)> a considerable digression from nominal operation.",
author = "Gorseth, {T. L.} and D. Estrada and J. Kiepert and Ogas, {M. L.} and Cheek, {B. J.} and Price, {P. M.} and Baker, {R. J.} and G. Bersuker and Knowlton, {W. B.}",
year = "2006",
doi = "10.1109/WMED.2006.1678294",
language = "English",
isbn = "142440374X",
series = "2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06",
pages = "31--32",
booktitle = "2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06",
note = "2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06 ; Conference date: 14-04-2006 Through 14-04-2006",
}