Preliminary study of NOR digital response to single pMOSFET dielectric degradation

T. L. Gorseth, D. Estrada, J. Kiepert, M. L. Ogas, B. J. Cheek, P. M. Price, R. J. Baker, G. Bersuker, W. B. Knowlton

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The voltage-time domain (VT) characteristics of the CMOS NOR logic circuit are investigated using a switch matrix technique (SMT). VT performance is analyzed following gate oxide wearout in a pMOSFET, induced by applying a constant voltage stress (CVS) at -4.0 V. Results for the NOR VT characteristics show approximately 30% increase in rise time (tr)> a considerable digression from nominal operation.

Original languageEnglish
Title of host publication2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06
Pages31-32
Number of pages2
DOIs
StatePublished - 2006
Event2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06 - Boise, ID, United States
Duration: 14 Apr 200614 Apr 2006

Publication series

Name2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06

Conference

Conference2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06
Country/TerritoryUnited States
CityBoise, ID
Period14/04/0614/04/06

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