Preliminary study of NOR digital response to single pMOSFET dielectric degradation

T. L. Gorseth; D. Estrada; J. Kiepert; M. L. Ogas; B. J. Cheek; P. M. Price; R. J. Baker; G. Bersuker; W. B. Knowlton

doi:10.1109/WMED.2006.1678294

Preliminary study of NOR digital response to single pMOSFET dielectric degradation

T. L. Gorseth
, D. Estrada
, J. Kiepert
, M. L. Ogas
, B. J. Cheek
, P. M. Price
, R. J. Baker
, G. Bersuker
, W. B. Knowlton

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The voltage-time domain (VT) characteristics of the CMOS NOR logic circuit are investigated using a switch matrix technique (SMT). VT performance is analyzed following gate oxide wearout in a pMOSFET, induced by applying a constant voltage stress (CVS) at -4.0 V. Results for the NOR VT characteristics show approximately 30% increase in rise time (t_r)> a considerable digression from nominal operation.

Original language	English
Title of host publication	2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06
Pages	31-32
Number of pages	2
DOIs	https://doi.org/10.1109/WMED.2006.1678294
State	Published - 2006
Event	2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06 - Boise, ID, United States Duration: 14 Apr 2006 → 14 Apr 2006

Publication series

Name	2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06

Conference

Conference	2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06
Country/Territory	United States
City	Boise, ID
Period	14/04/06 → 14/04/06

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10.1109/WMED.2006.1678294

Cite this

Gorseth, T. L., Estrada, D., Kiepert, J., Ogas, M. L., Cheek, B. J., Price, P. M., Baker, R. J., Bersuker, G., & Knowlton, W. B. (2006). Preliminary study of NOR digital response to single pMOSFET dielectric degradation. In 2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06 (pp. 31-32). Article 1678294 (2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06). https://doi.org/10.1109/WMED.2006.1678294

@inproceedings{a9f4ee42968f4dc4b8443aefec72e7c5,

title = "Preliminary study of NOR digital response to single pMOSFET dielectric degradation",

abstract = "The voltage-time domain (VT) characteristics of the CMOS NOR logic circuit are investigated using a switch matrix technique (SMT). VT performance is analyzed following gate oxide wearout in a pMOSFET, induced by applying a constant voltage stress (CVS) at -4.0 V. Results for the NOR VT characteristics show approximately 30\% increase in rise time (tr)> a considerable digression from nominal operation.",

author = "Gorseth, \{T. L.\} and D. Estrada and J. Kiepert and Ogas, \{M. L.\} and Cheek, \{B. J.\} and Price, \{P. M.\} and Baker, \{R. J.\} and G. Bersuker and Knowlton, \{W. B.\}",

year = "2006",

doi = "10.1109/WMED.2006.1678294",

language = "English",

isbn = "142440374X",

series = "2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06",

pages = "31--32",

booktitle = "2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06",

note = "2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06 ; Conference date: 14-04-2006 Through 14-04-2006",

}

Gorseth, TL, Estrada, D, Kiepert, J, Ogas, ML, Cheek, BJ, Price, PM, Baker, RJ, Bersuker, G & Knowlton, WB 2006, Preliminary study of NOR digital response to single pMOSFET dielectric degradation. in 2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06., 1678294, 2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06, pp. 31-32, 2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06, Boise, ID, United States, 14/04/06. https://doi.org/10.1109/WMED.2006.1678294

Preliminary study of NOR digital response to single pMOSFET dielectric degradation. / Gorseth, T. L.; Estrada, D.; Kiepert, J. et al.
2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06. 2006. p. 31-32 1678294 (2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Preliminary study of NOR digital response to single pMOSFET dielectric degradation

AU - Gorseth, T. L.

AU - Estrada, D.

AU - Kiepert, J.

AU - Ogas, M. L.

AU - Cheek, B. J.

AU - Price, P. M.

AU - Baker, R. J.

AU - Bersuker, G.

AU - Knowlton, W. B.

PY - 2006

Y1 - 2006

N2 - The voltage-time domain (VT) characteristics of the CMOS NOR logic circuit are investigated using a switch matrix technique (SMT). VT performance is analyzed following gate oxide wearout in a pMOSFET, induced by applying a constant voltage stress (CVS) at -4.0 V. Results for the NOR VT characteristics show approximately 30% increase in rise time (tr)> a considerable digression from nominal operation.

AB - The voltage-time domain (VT) characteristics of the CMOS NOR logic circuit are investigated using a switch matrix technique (SMT). VT performance is analyzed following gate oxide wearout in a pMOSFET, induced by applying a constant voltage stress (CVS) at -4.0 V. Results for the NOR VT characteristics show approximately 30% increase in rise time (tr)> a considerable digression from nominal operation.

UR - https://www.scopus.com/pages/publications/34250160903

U2 - 10.1109/WMED.2006.1678294

DO - 10.1109/WMED.2006.1678294

M3 - Conference contribution

AN - SCOPUS:34250160903

SN - 142440374X

SN - 9781424403745

T3 - 2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06

SP - 31

EP - 32

BT - 2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06

T2 - 2006 IEEE Workshop on Microelectronics and Electron Devices, WMED'06

Y2 - 14 April 2006 through 14 April 2006

ER -

Preliminary study of NOR digital response to single pMOSFET dielectric degradation

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