TY - GEN
T1 - Real-time bitstream decompression scheme for FPGAS reconfiguration
AU - Daoud, Luka
AU - Hussein, Fady
AU - Rafla, Nader
N1 - Publisher Copyright:
© 2018 IEEE
PY - 2018/7/2
Y1 - 2018/7/2
N2 - The state-of-the-art FPGAs require massive configuration files seeking on-chip large memory storage. Partial reconfigurable applications demand even more data storage for several additional partial bitstreams. To alleviate the memory storage requirements, bitstream compression techniques are needed. Efficient compression algorithms usually involve high complex hardware decompression circuits. This might increase the FPGA's (re)configuration time. In run-time reconfigurable applications, the required time of the decompression engine must be minimized. In this paper, we present a design and implementation of a newly developed bitstream decompression algorithm. The decompression circuit was implemented using Xilinx Vivado EDA design suite on a Zynq-based FPGA. While consuming only 118 CLB slices, 0.89% of the fabric, the decompression speed can reach the theoretical maximum reconfiguration frequency of 400 MB/s on 100 MHz clock as verified by hardware implementation. Furthermore, the effect of the FIFO buffer size and DMA configuration parameters on the decompression speed were studied.
AB - The state-of-the-art FPGAs require massive configuration files seeking on-chip large memory storage. Partial reconfigurable applications demand even more data storage for several additional partial bitstreams. To alleviate the memory storage requirements, bitstream compression techniques are needed. Efficient compression algorithms usually involve high complex hardware decompression circuits. This might increase the FPGA's (re)configuration time. In run-time reconfigurable applications, the required time of the decompression engine must be minimized. In this paper, we present a design and implementation of a newly developed bitstream decompression algorithm. The decompression circuit was implemented using Xilinx Vivado EDA design suite on a Zynq-based FPGA. While consuming only 118 CLB slices, 0.89% of the fabric, the decompression speed can reach the theoretical maximum reconfiguration frequency of 400 MB/s on 100 MHz clock as verified by hardware implementation. Furthermore, the effect of the FIFO buffer size and DMA configuration parameters on the decompression speed were studied.
KW - Field Programmable Gate Array (FPGA)
KW - High speed decompression
KW - Low cost decompression
KW - Partial bitstreams decompression
KW - Real-time bitstream decompression
UR - http://www.scopus.com/inward/record.url?scp=85062210428&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2018.8624003
DO - 10.1109/MWSCAS.2018.8624003
M3 - Conference contribution
AN - SCOPUS:85062210428
T3 - Midwest Symposium on Circuits and Systems
SP - 1082
EP - 1085
BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Y2 - 5 August 2018 through 8 August 2018
ER -