Real-time bitstream decompression scheme for FPGAS reconfiguration

Luka Daoud, Fady Hussein, Nader Rafla

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

The state-of-the-art FPGAs require massive configuration files seeking on-chip large memory storage. Partial reconfigurable applications demand even more data storage for several additional partial bitstreams. To alleviate the memory storage requirements, bitstream compression techniques are needed. Efficient compression algorithms usually involve high complex hardware decompression circuits. This might increase the FPGA's (re)configuration time. In run-time reconfigurable applications, the required time of the decompression engine must be minimized. In this paper, we present a design and implementation of a newly developed bitstream decompression algorithm. The decompression circuit was implemented using Xilinx Vivado EDA design suite on a Zynq-based FPGA. While consuming only 118 CLB slices, 0.89% of the fabric, the decompression speed can reach the theoretical maximum reconfiguration frequency of 400 MB/s on 100 MHz clock as verified by hardware implementation. Furthermore, the effect of the FIFO buffer size and DMA configuration parameters on the decompression speed were studied.

Original languageEnglish
Title of host publication2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1082-1085
Number of pages4
ISBN (Electronic)9781538673928
DOIs
StatePublished - 2 Jul 2018
Event61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018 - Windsor, Canada
Duration: 5 Aug 20188 Aug 2018

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2018-August
ISSN (Print)1548-3746

Conference

Conference61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Country/TerritoryCanada
CityWindsor
Period5/08/188/08/18

Keywords

  • Field Programmable Gate Array (FPGA)
  • High speed decompression
  • Low cost decompression
  • Partial bitstreams decompression
  • Real-time bitstream decompression

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