Reconfigurable Threshold Logic Gates Using Memristive Devices

Thanh Tran; Adrian Rothenbuhler; Elisa Barney Smith; Vishal Saxena; Kristy A. Campbell

doi:10.1109/SubVT.2012.6404301

Reconfigurable Threshold Logic Gates Using Memristive Devices

Thanh Tran
, Adrian Rothenbuhler
, Elisa Barney Smith
, Vishal Saxena
, Kristy A. Campbell

Electrical Engineering Department

Boise State University

Research output: Contribution to journal › Article › peer-review

14 Scopus citations

Abstract

We present our early design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using Silver-chalcogenide memristive devices combined with CMOS circuits. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in a Matlab-Simulink/Cadence co-simulation using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices.

Original language	American English
Journal	2012 IEEE Subthreshold Microelectronics Conference (SubVT)
DOIs	https://doi.org/10.1109/SubVT.2012.6404301
State	Published - 9 Oct 2012

Keywords

memristors
threshold logic circuits

EGS Disciplines

Electrical and Computer Engineering

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10.1109/SubVT.2012.6404301License: Unspecified

http://dx.doi.org/10.1109/SubVT.2012.6404301

Cite this

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title = "Reconfigurable Threshold Logic Gates Using Memristive Devices",

abstract = " We present our early design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using Silver-chalcogenide memristive devices combined with CMOS circuits. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in a Matlab-Simulink/Cadence co-simulation using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices.",

keywords = "memristors, threshold logic circuits",

author = "Thanh Tran and Adrian Rothenbuhler and \{Barney Smith\}, Elisa and Vishal Saxena and Campbell, \{Kristy A.\}",

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AU - Rothenbuhler, Adrian

AU - Barney Smith, Elisa

AU - Saxena, Vishal

AU - Campbell, Kristy A.

PY - 2012/10/9

Y1 - 2012/10/9

N2 - We present our early design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using Silver-chalcogenide memristive devices combined with CMOS circuits. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in a Matlab-Simulink/Cadence co-simulation using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices.

AB - We present our early design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using Silver-chalcogenide memristive devices combined with CMOS circuits. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in a Matlab-Simulink/Cadence co-simulation using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices.

KW - memristors

KW - threshold logic circuits

UR - https://scholarworks.boisestate.edu/electrical_facpubs/222

UR - http://dx.doi.org/10.1109/SubVT.2012.6404301

U2 - 10.1109/SubVT.2012.6404301

DO - 10.1109/SubVT.2012.6404301

M3 - Article

JO - 2012 IEEE Subthreshold Microelectronics Conference (SubVT)

JF - 2012 IEEE Subthreshold Microelectronics Conference (SubVT)

ER -

Reconfigurable Threshold Logic Gates Using Memristive Devices

Abstract

Keywords

EGS Disciplines

Access to Document

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