Reducing power consumption in FPGAs by pipelining

Reducing the logic levels in digital hardware designs can dramatically reduce power consumption of field-programmable gate arrays (FPGAs). In this study, logic levels were varied by applying different degrees of pipelining to five types of circuits: a parity circuit, two multipliers, an adder-based design, a sine-cosine generator, and an encryption circuit. Power was measured to the core logic of a 90-nm FPGA for each design. Results show that reducing the logic levels in a parity circuit can cut dynamic switching power by nearly a third, with no area expense. They also indicate that introducing pipeline registers can cut power by 44 percent to 83 percent in the other designs. In most cases, the reduction can be achieved with little or no area expense. In other cases, a noteworthy area tradeoff is required. The reduction can be attributed to the pipeline registers' ability to curb the number of useless signal transitions, or glitches. Reducing logic levels can reduce glitches by orders of magnitude, according to the results. The power-reduction techniques could be applied to many digital logic circuits and would be especially effective in compute-intensive designs.