TY - GEN
T1 - Routing aware and runtime detection for infected network-on-chip routers
AU - Daoud, Luka
AU - Rafla, Nader
N1 - Publisher Copyright:
© 2018 IEEE
PY - 2018/7/2
Y1 - 2018/7/2
N2 - Network-on-Chip (NoC) architecture is the communication heart of the processing cores in Multiprocessors System-on-Chip (MPSoC), where messages are routed from a source to a destination through intermediate nodes. Therefore, NoC has become a target to security attacks. By experiencing outsourcing design, NoC can be infected with a malicious Hardware Trojans (HTs) which potentially degrade the system performance or leave a backdoor for secret key leaking. In this paper, we propose a HT model that applies a denial of service attack by misrouting the packets, which causes deadlock and consequently degrading the NoC performance. We present a secure routing algorithm that provides a runtime HT detection and avoiding scheme. Results show that our proposed model has negligible overhead in area and power, 0.4% and 0.6%, respectively.
AB - Network-on-Chip (NoC) architecture is the communication heart of the processing cores in Multiprocessors System-on-Chip (MPSoC), where messages are routed from a source to a destination through intermediate nodes. Therefore, NoC has become a target to security attacks. By experiencing outsourcing design, NoC can be infected with a malicious Hardware Trojans (HTs) which potentially degrade the system performance or leave a backdoor for secret key leaking. In this paper, we propose a HT model that applies a denial of service attack by misrouting the packets, which causes deadlock and consequently degrading the NoC performance. We present a secure routing algorithm that provides a runtime HT detection and avoiding scheme. Results show that our proposed model has negligible overhead in area and power, 0.4% and 0.6%, respectively.
KW - Hardware Trojan
KW - Malicious-tolerant Routing Algorithm
KW - Network-on-Chip
KW - NoC
KW - Secure Routing Algorithm
UR - http://www.scopus.com/inward/record.url?scp=85062209794&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2018.8623972
DO - 10.1109/MWSCAS.2018.8623972
M3 - Conference contribution
AN - SCOPUS:85062209794
T3 - Midwest Symposium on Circuits and Systems
SP - 775
EP - 778
BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Y2 - 5 August 2018 through 8 August 2018
ER -