The effect of die attach voiding on the thermal resistance of chip level packages

Amy S. Fleischer, Li Hsin Chang, Barry C. Johnson

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

During semiconductor manufacturing, voids are easily formed in the die attach bond layer and are found to form, grow and coalesce with thermal cycling. The presence of such voids is known to adversely affect the package thermal resistance, but to this point, not enough data exists to precisely analyze the effects of void size, configuration and depth. Using an innovative experimental method the present study investigates these effects with a carefully controlled void geometry. The results show that the thermal resistance increases linearly with void percentage for random voids, but increases exponentially for contiguous voids.

Original languageEnglish
Title of host publicationProceedings of the ASME/Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems
Subtitle of host publicationAdvances in Electronic Packaging 2005
Pages299-304
Number of pages6
DOIs
StatePublished - 2005
Externally publishedYes
EventASME/Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems: Advances in Electronic Packaging 2005 - San Francisco, CA, United States
Duration: 17 Jul 200522 Jul 2005

Publication series

NameProceedings of the ASME/Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems: Advances in Electronic Packaging 2005
VolumePART A

Conference

ConferenceASME/Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems: Advances in Electronic Packaging 2005
Country/TerritoryUnited States
CitySan Francisco, CA
Period17/07/0522/07/05

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