The effect of die attach voiding on the thermal resistance of chip level packages

The presence of voids in the die bond region is known to adversely affect the thermal resistance of the packaged chip-level device. Unfortunately, such voids are easily formed in the solder layer during manufacturing, and are found to nucleate, grow and coalesce with thermal cycling. Although the relationship between package thermal resistance and voids has been examined extensively, little data exist concerning the precise effects of void size, configuration and position. The present study allows the experimental investigation of these effects through application of an innovative experimental technique that carefully controls void geometry and distribution. The results show that for small, random voids, the thermal resistance, θ_jc, increases linearly with void volume percentage, V_%, according to the equation θ_jc = 0.007V + 1.4987, and for large, contiguous voids the increase follows the exponential relationship, θ_jc = 1.427e^0.015V. At 73% voiding, θ_jc was found to increase 30% and 200% for random and contiguous voids, respectively.