TY - GEN
T1 - Thermo-mechanical analysis of thru-silicon-via based high density compliant interconnect
AU - Amnasalam, Parthiban
AU - Fan, Zhou
AU - Ackler, Harold D.
AU - Sammakia, Bahgat G.
PY - 2007
Y1 - 2007
N2 - In this paper, detailed 3D FEM thermo-mechanical analysis is performed on a chip stack that utilizes the Smart Three Axis Compliant (STAC) interconnect, a TSV based ultra-high density compliant interconnect. These interconnects are microstructurally engineered to accommodate relative displacements between ultra-thin TSV based silicon chips and substrates to which they are bonded without transferring significant stress to the die itself. The paper will first cover 3D numerical model of the TiW bi-metal layer compliant beam built with opposing stresses to establish z-axis lift-height that compares well with analytical results. With this validated model, a force-deflection curve is established for a 125μm×25μm×0.8μm TiW free beam with 1GPa stress built into its two metal layers (-500MPa in the bottom layer and +500MPa in the top layer). This will enable numerical characterization of the compliancy of a single interconnect. This analysis is followed by thermo-mechanical analysis of a unit cell STAC interconnect (TSV, copper bond pad and the compliant beam) built on a 50μm thick silicon die. Particular attention is given to stresses formed in the TSV copper column when temperature is varied from -40°C to 150°C. Finally experimental results performed on a successfully fabricated STAC interconnect based Si-Glass stacked die is presented and a numerical model of this chip stack is built to capture the top ultra-thin glass die deformation when temperature is varied from 20°C to 130°C.
AB - In this paper, detailed 3D FEM thermo-mechanical analysis is performed on a chip stack that utilizes the Smart Three Axis Compliant (STAC) interconnect, a TSV based ultra-high density compliant interconnect. These interconnects are microstructurally engineered to accommodate relative displacements between ultra-thin TSV based silicon chips and substrates to which they are bonded without transferring significant stress to the die itself. The paper will first cover 3D numerical model of the TiW bi-metal layer compliant beam built with opposing stresses to establish z-axis lift-height that compares well with analytical results. With this validated model, a force-deflection curve is established for a 125μm×25μm×0.8μm TiW free beam with 1GPa stress built into its two metal layers (-500MPa in the bottom layer and +500MPa in the top layer). This will enable numerical characterization of the compliancy of a single interconnect. This analysis is followed by thermo-mechanical analysis of a unit cell STAC interconnect (TSV, copper bond pad and the compliant beam) built on a 50μm thick silicon die. Particular attention is given to stresses formed in the TSV copper column when temperature is varied from -40°C to 150°C. Finally experimental results performed on a successfully fabricated STAC interconnect based Si-Glass stacked die is presented and a numerical model of this chip stack is built to capture the top ultra-thin glass die deformation when temperature is varied from 20°C to 130°C.
UR - http://www.scopus.com/inward/record.url?scp=35348890136&partnerID=8YFLogxK
U2 - 10.1109/ECTC.2007.373943
DO - 10.1109/ECTC.2007.373943
M3 - Conference contribution
AN - SCOPUS:35348890136
SN - 1424409853
SN - 9781424409853
T3 - Proceedings - Electronic Components and Technology Conference
SP - 1179
EP - 1185
BT - Proceedings - 57th Electronic Components and Technology Conference 2007, ECTC '07
T2 - 57th Electronic Components and Technology Conference 2007, ECTC '07
Y2 - 29 May 2007 through 1 June 2007
ER -