Through wafer interconnects for 3-D packaging

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Semiconductor technology has reached a point in its evolution where the package now plays an important role in the overall performance of the device. In MEMs devices, the package is often more than 75% of the cost and has a significant impact in the overall size. Through wafer interconnects allow for advanced 3-D packaging schemes. Additional miniaturization, increased interconnection density, and higher performance is possible by stacking die with through wafer interconnects. Key technologies for creating TWIs are the ability to create a via through the silicon wafer, dielectric isolation of the via metal from the substrate, and filling or coating the via with a conducting material. Through wafer interconnects have been demonstrated in silicon wafers. The process to create TWIs has been optimized. The TWI has been tested electrically and proven reliable. TWIs were incorporated into an active device wafer and a two die stack connected through solder bump technology. In current work, specific applications which take advantage of the benefits of TWI's are being explored including 3-D inductors, unique sensor packages and MEMs applications.

Original languageEnglish
Title of host publicationEnabling Technologies for 3-D Integration
Pages163-169
Number of pages7
StatePublished - 2007
Event2006 MRS Fall Meeting - Boston, MA, United States
Duration: 27 Nov 200629 Nov 2006

Publication series

NameMaterials Research Society Symposium Proceedings
Volume970
ISSN (Print)0272-9172

Conference

Conference2006 MRS Fall Meeting
Country/TerritoryUnited States
CityBoston, MA
Period27/11/0629/11/06

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