TY - GEN
T1 - Through wafer interconnects for 3-D packaging
AU - Moll, Amy J.
AU - Knowlton, William B.
AU - Oxford, Rex
PY - 2007
Y1 - 2007
N2 - Semiconductor technology has reached a point in its evolution where the package now plays an important role in the overall performance of the device. In MEMs devices, the package is often more than 75% of the cost and has a significant impact in the overall size. Through wafer interconnects allow for advanced 3-D packaging schemes. Additional miniaturization, increased interconnection density, and higher performance is possible by stacking die with through wafer interconnects. Key technologies for creating TWIs are the ability to create a via through the silicon wafer, dielectric isolation of the via metal from the substrate, and filling or coating the via with a conducting material. Through wafer interconnects have been demonstrated in silicon wafers. The process to create TWIs has been optimized. The TWI has been tested electrically and proven reliable. TWIs were incorporated into an active device wafer and a two die stack connected through solder bump technology. In current work, specific applications which take advantage of the benefits of TWI's are being explored including 3-D inductors, unique sensor packages and MEMs applications.
AB - Semiconductor technology has reached a point in its evolution where the package now plays an important role in the overall performance of the device. In MEMs devices, the package is often more than 75% of the cost and has a significant impact in the overall size. Through wafer interconnects allow for advanced 3-D packaging schemes. Additional miniaturization, increased interconnection density, and higher performance is possible by stacking die with through wafer interconnects. Key technologies for creating TWIs are the ability to create a via through the silicon wafer, dielectric isolation of the via metal from the substrate, and filling or coating the via with a conducting material. Through wafer interconnects have been demonstrated in silicon wafers. The process to create TWIs has been optimized. The TWI has been tested electrically and proven reliable. TWIs were incorporated into an active device wafer and a two die stack connected through solder bump technology. In current work, specific applications which take advantage of the benefits of TWI's are being explored including 3-D inductors, unique sensor packages and MEMs applications.
UR - http://www.scopus.com/inward/record.url?scp=34250875626&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:34250875626
SN - 1558999272
SN - 9781558999275
T3 - Materials Research Society Symposium Proceedings
SP - 163
EP - 169
BT - Enabling Technologies for 3-D Integration
T2 - 2006 MRS Fall Meeting
Y2 - 27 November 2006 through 29 November 2006
ER -